1. Field of the Invention
The present invention relates to an optical repeater useful for optical trunk transmission systems, and more particularly to a bit rate-selective type optical regenerative repeater which automatically discriminates the transmission rate and repeats optical signals accordingly.
2. Description of the Related Art
In a large capacity optical communications system, the bit rate of transmitted signals is selected according to the purpose of use out of a number of alternatives standardized as SDH. Therefore, for economical system architecture, it is desirable that the optical repeater to be installed in the system be operable at all bit rates.
According to the prior art, optical regenerating repeaters of bit rate-independent type used for repeating of optical signals have only one or two of the so-called 3R functions (reshaping, retiming and regenerating), but not the retiming function. Such an optical regenerative repeater shapes the waveform without regenerating timing clock signals from the received optical signals, and converts the received signals into optical signals to be outputted. As a result, it regenerates and repeats not only the optical signals as such but also noise. Therefore, the signal waveform and above all the duty ratio of digital signals are deteriorated, resulting in an adverse effect on transmission characteristics.
To avert this problem, a configuration in which optical signals modulated with a clock signal synchronized with data signals are transmitted over a separate path from that for optical signals modulated with data signals is proposed. However, such bit rate-independent type optical regenerative repeaters according to the prior art are both expensive and unreliable, because they require duplication of the optical transmitting/receiving circuit to transfer clock signals separately from data signals. Where data signals and clock signals are transmitted over the same optical fiber path to reduce the cost of the path, wavelength division multiplexing (WDM) is required, resulting in the problem that, if such an optical regenerative repeater is to be extended into a WDM transmission system, the optical wavelength band cannot be effectively used.
An object of the present invention is to provide an inexpensive bit rate-selective type optical regenerative repeater compatible with a plurality of bit rates and not wasteful in the use of an optical wavelength band.
According to the invention, there is provided a bit rate-selective type optical regenerative repeater provided with a photoelectric converter, a bit rate-selective type discriminator/ regenerator and an electro-optical converter, wherein: the photoelectric converter converts input an optical signal into an electric signal; the bit rate-selective type discriminator/regenerator discriminates and regenerates the electric signal which is entered; and the electro-optical converter converts the discriminated/regenerated signal supplied from the bit rate-selective type discriminator/regenerator into an optical signal.
The bit rate-selective type discriminator/regenerator has a bit rate-selective type timing extractor and a discriminating circuit. The bit rate-selective type timing extractor extracts a timing component from an input digital signal. The discriminating circuit discriminates and regenerates the input digital signal with the timing component.
The bit rate-selective discriminator/regenerator may as well be provided with a phase-locked loop (PLL) circuit, a discriminating circuit, a specific pattern detecting circuit and a control circuit. The PLL circuit multiplies the clock component in the input digital signal by a factor set on the basis of a multiplying factor selection signal entered from outside, and supplies a resultant multiplied clock signal. The discriminating circuit discriminates and regenerates the input digital signal with the multiplied clock signal, and supplies a resultant discriminated/regenerated signal. The specific pattern detecting circuit checks the discriminated/regenerated signal as to whether or not it has a specific pattern inserted into the input digital signal in advance, and supplies the result of checking as detection signal. The control circuit, into which the detection signal is entered, generates and supplies the multiplying factor selection signal to vary the multiplying factor successively until any of the detection signals indicates the presence of the specific pattern.
Alternatively, the bit rate-selective discriminator/regenerator may be provided with a differentiating circuit, a rectifying circuit, a band-pass filter, a frequency dividing circuit, a specific pattern detecting circuit and a control circuit. The differentiating circuit, into which the input digital signal is entered, supplies a pulse signal at a varying point of the input digital signal. The rectifying circuit accomplishes full-wave rectification of the pulse signal, and supplies a rectified pulse signal. The band-pass filter passes harmonics of the clock component of the input digital signal contained in the rectified pulse signal. The frequency dividing circuit frequency-divides the harmonics, which are entered into it, by a ratio set on the basis of the multiplying factor selection signal, and supplies a resultant frequency-divided clock signal. The discriminating circuit discriminates and regenerates the input digital signal with the frequency-divided clock signal, and supplies a resultant discriminated/regenerated signal. The specific pattern detecting circuit checks the discriminated/regenerated signal as to whether or not it has a specific pattern inserted into the input digital signal in advance, and supplies the result of checking as detection signal. The control circuit, into which the detection signal is entered, generates and supplies the multiplying factor selection signal to vary the frequency dividing ratio successively until any of the detection signals indicates the presence of the specific pattern.
The bit rate-selective timing extractor is provided with an automatic bit rate discriminator and a PLL circuit. The automatic bit rate discriminator calculates the bit rate of an input digital signal, and supplies a multiplying factor selection signal. The PLL circuit multiplies the clock component in the input digital signal by a factor set on the basis of the multiplying factor selection signal entered from outside, and supplies a resultant multiplied clock signal.
The bit rate-selective type timing extractor may as well be provided with an automatic bit rate discriminator, a differentiating circuit, a rectifying circuit, a band pass filter, and a frequency dividing circuit. The automatic bit rate discriminator calculates the bit rate of an input digital signal, and supplies a multiplying factor selection signal. The differentiating circuit, into which the input digital signal is entered, supplies a pulse signal at a varying point of the input digital signal. The rectifying circuit accomplishes full-wave rectification of the pulse signal, and supplies a rectified pulse signal. The band-pass filter passes harmonics of the clock component of the input digital signal contained in the rectified pulse signal. The frequency dividing circuit frequency-divides the harmonics, which are entered into it, by a ratio set on the basis of the multiplying factor selection signal, and supplies a resultant frequency-divided clock signal.
Alternatively, the bit rate-selective type timing extractor may be provided with a plurality of timing extracting circuits set to extract mutually different frequencies, a selector circuit, and a selection control circuit. Each of the timing extracting circuits is provided with a differentiating circuit, a rectifying circuit, a band-pass filter and a power detecting circuit. The differentiating circuit, into which the digital signal is entered, supplies a pulse signal at a varying point of the input digital signal. The rectifying circuit accomplishes full-wave rectification of the pulse signal, and supplies a rectified pulse signal. The band-pass filter, into which the rectified pulse signal is entered, selectively supplies a sine wave signal having a predetermined frequency. The power detecting circuit, into which the sine wave signal is entered, supplies a power signal having a parameter which varies monotonously with the input signal power. The plurality of timing extracting circuits are set to different predetermined frequencies. The selecting circuit, into which the sine wave signals are entered, selects one of the input signals in accordance with a selection signal entered from outside, and supplies the selected sine wave signal. The selection control circuit, into which the power signals are entered, generates the selection signal for selecting the sine wave signal having the greatest power, and feeds it to the selecting circuit.
The automatic bit rate discriminator is provided with a counter and a bit rate detector. The counter counts for a prescribed period of time the number of bits having one of two levels of bits constituting the digital signals which are entered, and supplies a count signal. The bit rate detector calculates the bit rate of the digital signals from the count signal.
The automatic bit rate discriminator may as well be provided with a counter and a one bit length detecting circuit. The counter, into which a digital signal and a clock signal having a frequency not lower than the bit rate of the digital signal are entered, measures the duration of one of two levels of bits constituting the digital signal in terms of the number of cycles of the clock, and supplies it as bit length signal. The one bit length detecting circuit, into which the bit length signal is entered, calculates the shortest duration of the one of two levels.